Developed EDA flow for asynchronous chips, called Loom (see projects). Built a lecture series on asynchronous circuit design (see teaching), and taught this lecture series twice to small groups. Created many circuit modules required for a reconfigurable array chip architecture. Formed business, submitted proposals to NSF Seed Fund, Activate, NASA SBIR, and DIU, and whitepapers for other BAAs and granting opportunities. Created financial and manufacturing models for chip tapeout. Continuous outreach to local hard-tech communities.
Increased the scalability of the content delivery scheduling system by two orders of magnitude. Designed and implemented the event processing system including real-time evaluation of 20 different KPIs and management of dataflow for analytics. Organized and mediated review of five major system architecture specifications as head of the Architecture Review Board. These systems formed the fundamental backbone of the final product.
Developed the emoji picker in 2018 for chat.google.com including front and back end design. Designed and implemented a complete development environment and circuit library for self-timed circuits in 2016 with automatic test generation and mixed-signal simulation.
Corporate Finance Academy, Kelley Merit Fellow, Entrepreneurial Innovation Academy, Elevate Ventures Challenge First Place
Analyzed statistical behavior of program workload for optimizable features, invented a collection of arithmetic operators using those program workload features that doubled throughput per transistor and halved energy per operation on average compared to industry standard approaches.
Developed an automated formal synthesis engine for Quasi-Delay Insensitive circuits including a simulator, state space elaborator, and state conflict checker for Handshaking Expansions along with partial implementations for unique state encoding and guard strengthening.
A full EDA toolset for Quasi-Delay Insensitive circuits including high level synthesis of complex state machines, simulation, automated sizing, netlisting, cell generation, cell library management, automated cell layout, extraction, and layout vs schematic. Circuits are described as an abstract behavioral model in Communicating Hardware Processes (CHP) and formal transformations are applied to synthesize a digital circuit.
Collaborated on the tapeout of the Braindrop chip, and was responsible for the design, verification, and layout of the asynchronous memory.
A rendering engine for large randomly generated planets with smooth level-of-detail transition from space to ground.
A full container library implemented as an educational exercise, implementing generic slices using any container of iterators.
A library for fast many-variable boolean logic synthesis.
A recipe website that calculates the ingredients that are more likely to be in a recipe with the ingredients already selected.
Four small neuron toys that can be connected together to form a simple neural network. Upon firing, a set of LEDs along the axon and dendrites light up in sequence to show a depolarization travel from one neuron to the next.
VLSI, Digital Logic, Verilog, Spice, Place & Route, Floor Planning, Java, Python, Perl, Matlab, SQL, Specman E (verification), Git, Slurm, Cadence Virtuoso, Magic VLSI, Blender, 3DS Max, Maya, Compilers, Distributed Systems, Flink, Terraform, Ansible, MongoDB, Redis, AWS, Gitlab CI, Kafka, GRPC, Go, Grafana, Datadog, Protobufs, Docker, Kubernetes