Developed the key Intellectual Property for the first product, developed a course on self timed circuits to bootstrap the hiring pipeline, developed a thorough value proposition through in-depth market research, wrote a grant to the NSF Seed Fund, developed a full three statement financial model to project viability of the business, and continuous networking for customer relationship and customer product validation.
Mentored and managed six team members. Three were promoted to leadership roles and are now managing small teams while owning and developing major subsystems of the product. Designed, and implemented a system for routing user requests in a large scale Content Distribution Network (CDN), a major feature required for final product functionality. Deployed the staging and production clusters with a cross-functional team finalizing the product allowing the rest of the engineering org to push updates to production through CI/CD processes.
Organized and mediated review of five major system architecture specifications as head of the Architecture Review Board. These systems formed the fundamental backbone of the final product. Analyzed steady state behavior of the content delivery scheduling system for optimization and led a significant effort that increased its scalability by two orders of magnitude. Designed and implemented the event processing system including real-time evaluation of 20 different KPIs and management of dataflow for analytics.
Corporate Finance Academy, Kelley School of Business Merit Fellowship Award
Analyzed statistical behavior of program workload for optimizable features, invented a collection of arithmetic operators using those program workload features that doubled throughput per transistor and halved energy per operation on average compared to industry standard approaches.
Developed an automated formal synthesis engine for Quasi-Delay Insensitive circuits including a simulator, state space elaborator, and state conflict checker for Handshaking Expansions along with partial implementations for unique state encoding and guard strengthening.
Collaborated on the tapeout of the Braindrop chip, and was responsible for the design, verification, and layout of the asynchronous memory.
A synthesis engine for Quasi-Delay Insensitive circuits. Circuits are described as an abstract behavioral model in Communicating Hardware Processes (CHP) and formal transformations are applied to synthesize a digital circuit.
A rendering engine for large randomly generated planets with smooth level-of-detail transition from space to ground.
A full container library implemented as an educational exercise, implementing generic slices using any container of iterators.
Four small neuron toys that can be connected together to form a simple neural network. Upon firing, a set of LEDs along the axon and dendrites light up in sequence to show a depolarization travel from one neuron to the next.
Managed the interactions between the flight computer and the sensors, keeping track of data formats, data transfer speeds, and sensor health.
VLSI, Digital Logic, Verilog, Spice, Place & Route, Floor Planning, Java, Python, Perl, Matlab, SQL, Specman E (verification), Git, Slurm, Cadence Virtuoso, Magic VLSI, Blender, 3DS Max, Maya, Compilers, Distributed Systems, Flink, Terraform, Ansible, MongoDB, Redis, AWS, Gitlab CI, Kafka, GRPC, Go, Grafana, Datadog, Protobufs, Docker, Kubernetes